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4K
X5043/X5045
CPU Supervisor with 4K SPI EEPROM
512 x 8 Bit
FEATURES * Selectable time out watchdog timer * Low VCC detection and reset assertion --Five standard reset threshold voltages --Re-program low VCC reset threshold voltage using special programming sequence. --Reset signal valid to VCC = 1V * Long battery life with low power consumption --<50A max standby current, watchdog on --<10A max standby current, watchdog off --<2mA max active current during read * 2.7V to 5.5V and 4.5V to 5.5V power supply versions * 4Kbits of EEPROM-1M write cycle endurance * Save critical data with Block LockTM memory --Protect 1/4, 1/2, all or none of EEPROM array * Built-in inadvertent write protection --Write enable latch --Write protect pin * 3.3MHz clock rate * Minimize programming time --16-byte page write mode --Self-timed write cycle --5ms write cycle time (typical) * SPI modes (0,0 & 1,1) * Available packages --8-lead MSOP, 8-lead SOIC, 8-pin PDIP --14-lead TSSOP BLOCK DIAGRAM
Watchdog Transition Detector WP SI SO SCK Data Register Command Decode & Control Logic VCC Threshold Reset Logic
DESCRIPTION These devices combine four popular functions, Poweron Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/ RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device's low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Xicor's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.
Watchdog Timer Reset
Protect Logic RESET/RESET Status Register EEPROM Array 1Kbits 1Kbits 2Kbits Reset & Watchdog Timebase X5043 = RESET X5045 = RESET
CS/WDI
VCC VTRIP
+ -
Power on and Low Voltage Reset Generation
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The memory portion of the device is a CMOS Serial EEPROM array with Xicor's block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. PIN CONFIGURATION
8-Lead SOIC/PDIP/MSOP CS/WDI SO WP VSS 1 2 3 4 X5043/45 8 7 6 5 VCC RESET/RESET SCK SI
Chip Select (CS) When CS is high, the X5043/45 is deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X5043/45 will be in the standby power mode. CS low enables the X5043/45, placing it in the active power mode. It should be noted that after power-up, a high to low transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is low, nonvolatile writes to the X5043/45 are disabled, but the part otherwise functions normally. When WP is held high, all functions, including non volatile writes operate normally. WP going low while CS is still low will interrupt a write to the X5043/45. If the internal write cycle has already been initiated, WP going low will have no affect on a write. Reset (RESET, RESET) X5043/45, RESET/RESET is an active low/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET also goes active if the Watchdog timer is enabled and CS remains either high or low longer than the Watchdog time out period. A falling edge of CS will reset the watchdog timer. PIN NAMES Symbol Description
Chip Select Input Serial Output Serial Input Serial Clock Input Write Protect Input Ground Supply Voltage Reset Output
14-Lead TSSOP CS SO NC NC NC WP VSS 1 2 3 4 5 6 7 X5043/45 14 13 12 11 10 9 8 VCC RESET/RESET NC NC NC SCK SI
PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the falling edge of the clock input.
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CS SO SI SCK WP VSS VCC RESET/RESET
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PRINCIPLES OF OPERATION Power On Reset Application of power to the X5043/X5045 activates a Power On Reset Circuit. This circuit pulls the RESET/ RESET pin active. RESET/RESET prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET/RESET, allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X5043/X5045 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent an active RESET/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits. With no microprocessor action, the watchdog timer control bits remain unchanged, even during total power failure. VCC Threshold Reset Procedure The X5043/X5045 is shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X5043/X5045 threshold may be adjusted. The procedure is described below, and uses the application of a high voltage control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new VTRIP voltage, apply the desired VTRIP threshold voltage to the VCC pin and tie the WP pin to the programming voltage VP. Then send a WREN command, followed by a write of Data 00h to address 01h. CS going HIGH on the write operation initiates the VTRIP programming sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 01h.
Figure 1. Set VTRIP Level Sequence (VCC = desired VTRIP value.)
WP VPE = 15-18V
CS 01234567 SCK 8 Bits SI 06h WREN 02h Write 01h Address 00h Data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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Resetting the VTRIP Voltage This procedure is used to set the VTRIP to a "native" voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the VTRIP voltage, apply at least 3V to the VCC pin and tie the WP pin to the programming voltage VP. Then send a WREN command, followed by a write of Data 00h to address 03h. CS going HIGH on the write operation initiates the VTRIP programming sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 03h.
Figure 2. Reset VTRIP Level Sequence (VCC > 3V. WP = 15-18V)
WP VPE = 15-18V
CS 01234567 SCK 8 Bits SI 06h WREN 02h Write 03h Address 00h Data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 3. Sample VTRIP Reset Circuit
4.7K VP Adjust VTRIP Adj. 1 2 3 4 X5043 X5045 8 7 6 5 RESET C
SCK SI SO CS
Run
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Figure 4. VTRIP Programming Sequence
VTRIP Programming
Execute Reset VTRIP Sequence
SPI Serial Memory The memory portion of the device is a CMOS Serial EEPROM array with Xicor's block lock protection. The array is internally organized as x8 bits. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years.
Set VCC = VCC Applied = Desired VTRIP New VCC Applied = Old VCC Applied - Error New VCC Applied = Old VCC Applied - Error
Execute Set VTRIP Sequence Apply 5V to VCC
The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The device contains an 8-bit instruction register that controls the operation of the device. The instruction code is written to the device via the SI input. There are two write operations that requires only the instruction byte. There are two read operations that use the instruction byte to initiate the output of data. The remainder of the operations require an instruction byte, an 8-bit address, then data bytes. All instruction, address and data bits are clocked by the SCK input. All instructions (Table 1), addresses and data are transferred MSB first. Clock and Data Timing Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. CS must be LOW during the entire operation.
Execute Reset VTRIP Sequence
Decrement VCC (VCC = VCC-10mV)
NO
RESET pin goes active? YES Measured VTRIP -Desired VTRIP
Error -Emax
Error Emax
-Emax < Error < Emax DONE Emax = Maximum Desired Error
Table 1. Instruction Set Instruction Name
WREN WRDI RSDR WRSR READ WRITE
Note:
Instruction Format*
0000 0110 0000 0100 0000 0101 0000 0001 0000 A8011 0000 A8010
Operation
Set the Write Enable Latch (Enable Write Operations) Reset the Write Enable Latch (Disable Write Operations) Read Status Register Write Status Register (Watchdog and Block Lock) Read Data from Memory Array Beginning at Selected Address Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
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Write Enable Latch The device contains a Write Enable Latch. This latch must be SET before a Write Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 3). This latch is automatically reset upon a power-up condition and after the completion of a valid byte, page, or status register write cycle. The latch is also reset if WP is brought LOW. When issuing a WREN, WRDI or RDSR commands, it is not necessary to send a byte address or data. Figure 5. Write Enable/Disable Latch Sequence
CS
The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any portion of the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory. Status Reg Bits BL1
0 0 1 1
Array Addresses Protected X5043/X5045
None $180-$1FF $100-$1FF $000-$1FF
BL0
0 1 0 1
0 SCK
1
2
3
4
5
6
7
The Watchdog Timer bits, WD0 and WD1, select the Watchdog Time-out Period. These nonvolatile bits are programmed with the WRSR instruction. Status Register Bits WD1 WD0
0 1 0 1
SI High Impedance
Watchdog Time Out (Typical)
1.4 seconds 600 milliseconds 200 milliseconds disabled (factory default)
SO
0 0 1 1
Status Register The Status Register contains four nonvolatile control bits and two volatile status bits. The control bits set the operation of the watchdog timer and the memory block lock protection. The Status Register is formatted as shown in "Status Register". Status Register: (Default = 30H) 7
0
6
0
5
4
3
BL1
2
BL0
1
WEL
0
WIP
WD1 WD0
Read Status Register To read the Status Register, pull CS low to select the device, then send the 8-bit RDSR instruction. Then the contents of the Status Register are shifted out on the SO line, clocked by CLK. Refer to the Read Status Register Sequence (Figure 6). The Status Register may be read at any time, even during a Write Cycle. Write Status Register Prior to any attempt to write data into the status register, the "Write Enable" Latch (WEL) must be set by issuing the WREN instruction (Figure 5). First pull CS LOW, then clock the WREN instruction into the device and pull CS HIGH. Then bring CS LOW again and enter the WRSR instruction followed by 8 bits of data. These 8 bits of data correspond to the contents of the status register. The operation ends with CS going HIGH. If CS does not go HIGH between WREN and WRSR, the WRSR instruction is ignored.
The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a "1", a nonvolatile write operation is in progress. When set to a "0", no write is in progress. The Write Enable Latch (WEL) bit indicates the status of the "write enable" latch. When WEL = 1, the latch is set and when WEL = 0 the latch is reset. The WEL bit is a volatile, read only bit. The WREN instruction sets the WEL bit and the WRDS instruction resets the WEL bit.
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Table 2. Device Protect Matrix WREN CMD (WEL)
0 x 1
Device Pin (WP)
x 0 1
Memory Block Protected Area
Protected Protected Protected
Status Register (BL0, BL1, WD0, WD1)
Protected Protected Writable
Unprotected Area
Protected Protected Writable
Figure 6. Read Status Register Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Instruction SI Data Out 7 MSB 6 5 4 3 2 1 0
SO
High Impedance
Figure 7. Write Status Register Sequence
CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction SI 7 6 5
Data Byte 4 3 2 1 0
SO
High Impedance
Read Memory Array When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 8-bit address. Bit 3 of the READ instruction selects the upper or lower half of the device. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next
address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the Read EEPROM Array Sequence (Figure 8).
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Figure 8. Read EEPROM Array Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
12 13 14 15 16 17
18 19 20 21 22
Instruction SI 8 7 6
8 Bit Address 5 3 2 1 0
9th Bit of Address High Impedance SO 7 MSB 6 5 4
Data Out 3 2 1 0
Write Memory Array Prior to any attempt to write data into the memory array, the "Write Enable" Latch (WEL) must be set by issuing the WREN instruction (Figure 5). First pull CS LOW, then clock the WREN instruction into the device and pull CS HIGH. Then bring CS LOW again and enter the WRITE instruction followed by the 8-bit address and then the data to be written. Bit 3 of the WRITE instruction contains address bit A8, which selects the upper or lower half of the array. If CS does not go HIGH between WREN and WRITE, the WRITE instruction is ignored. The WRITE operation requires at least 16 clocks. CS must go low and remain low for the duration of the operation. The host may continue to write up to 16 bytes of data. The only restriction is that the 16 bytes
must reside within the same page. A page address begins with address [x xxxx 0000] and ends with [x xxxx 1111]. If the byte address reaches the last byte on the page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that has been previously written. For the write operation (byte or page write) to be completed, CS must be brought HIGH after bit 0 of the last complete data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 9). While the write is in progress following a status register or memory array write sequence, the Status Register may be read to check the WIP bit. WIP is HIGH while the nonvolatile write is in progress.
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Figure 9. Write Memory Sequence
CS 0 SCK Instruction SI 8 7 6 8 Bit Address 5 32 Data Byte 1 4321 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23
1
0
7
6
5
0
9th Bit of Address
CS 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK Data Byte 2 5432 Data Byte 3 5432 Data Byte N 4321
SI
7
6
1
0
7
6
1
0
6
5
0
OPERATIONAL NOTES The device powers-up in the following state: - The device is in the low power standby state. - A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. - SO pin is high impedance. - The Write Enable Latch is reset. - The Flag Bit is reset. - Reset Signal is active for tPURST.
Data Protection The following circuitry has been included to prevent inadvertent writes: - A WREN instruction must be issued to set the Write Enable Latch. - CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle. - Block Protect bits provide additional level of write protection for the memory array. - The WP pin LOW blocks nonvolatile write operations.
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ABSOLUTE MAXIMUM RATINGS Temperature under bias ....................-65C to +135C Storage temperature ........................-65C to +150C Voltage on any pin with respect to VSS ...................................... -1.0V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds).........300C COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temperature
Commercial Industrial
Min.
0C -40C
Max.
70C +85C
Option
-2.7, -2.7A Blank, -4.5A
Supply Voltage Limits
2.7V to 5.5V 4.5V to 5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol
ICC1 ICC2 ISB1 ISB2 ILI ILO VIL
(1) (1)
Parameter
VCC Write Current (Active) VCC Read Current (Active) VCC Standby Current WDT = OFF VCC Standby Current WDT = ON Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage (SO) Output HIGH Voltage (SO) Output HIGH Voltage (SO) Output HIGH Voltage (SO) Output LOW Voltage (RESET, RESET)
Min.
Typ.(2)
Max.
3 2 10 50
Unit
mA mA A A A A V V V V V V
Test Conditions/Comments
SCK = 3.3MHz(3); SO, RESET, RESET = Open SCK = 3.3MHz(3); SI = VSS, RESET, RESET = Open CS = VCC, SCK, SI = VSS, VCC = 5.5V CS = VCC, SCK, SI = VSS, VCC = 5.5V SCK, SI, WP = VSS to VCC SO, RESET, RESET = VSS to VCC SCK, SI, WP, CS SCK, SI, WP, CS IOL = 2mA @ VCC = 2.7V IOL = 0.5mA @ VCC = 1.8V VCC > 3.3V, IOH = -1.0mA 2V < VCC 3.3V, IOH = -0.4mA VCC 2V, IOH = -0.25mA IOL = 1mA
0.1 0.1 -0.5 VCC x 0.7
10 10 VCC x 0.3 VCC + 0.5 0.4
VIH
VOL VOH1 VOH2 VOH3 VOLRS
VCC - 0.8 VCC - 0.4 VCC - 0.2 0.4
V
CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V Symbol
COUT CIN
(2) (2)
Test
Output Capacitance (SO, RESET, RESET) Input Capacitance (SCK, SI, CS, WP)
Max.
8 6
Unit
pF pF
Conditions
VOUT = 0V VIN = 0V
Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. (3) SCK frequency measured from VCC x 0.1/VCC x 0.9 REV 1.1.2 5/29/01
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Equivalent A.C. Load Circuit at 5V VCC
5V 5V 4.6K
A.C. Test Conditions
Input pulse levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x0.5
1.64K Output 1.64K 30pF RESET/RESET
30pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing 2.7V-5.5V Symbol
fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI tFI
(3) (3)
Parameter
Clock Frequency Cycle Time CS Lead Time CS Lag Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Input Rise Time Input Fall Time CS Deselect Time Write Cycle Time
Min.
0 300 150 150 130 130 30 30
Max.
3.3
Unit
MHz ns ns ns ns ns ns ns
2 2 100 10
s s ns ms
tCS tWC(4)
Data Output Timing 2.7-5.5V Symbol
fSCK tDIS tV tHO tRO tFO
(3) (3)
Parameter
Clock Frequency Output Disable Time Output Valid from Clock Low Output Hold Time Output Rise Time Output Fall Time
Min.
0
Max.
3.3 150 120
Unit
MHz ns ns ns ns ns
0 50 50
Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
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Serial Output Timing
CS tCYC SCK tV SO MSB Out MSB-1 Out tHO tWL LSB Out tDIS tWH tLAG
SI
ADDR LSB IN
Serial Input Timing
tCS CS tLEAD SCK tSU SI MSB In tH tRI
tFI
tLAG
LSB In
High Impedance SO
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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Power-Up and Power-Down Timing
VCC VTRIP 0 Volts tR RESET (X5043) tPURST tPURST tF tRPD VTRIP
RESET (X5045)
RESET Output Timing Symbol
VTRIP
Parameter
Reset Trip Point Voltage, (-4.5A) Reset Trip Point Voltage, (Blank) Reset Trip Point Voltage, (-2.7A) Reset Trip Point Voltage, (-2.7) Power-up Reset Time Out VCC Detect to Reset/Output VCC Fall Time VCC Rise Time Reset Valid VCC
Min.
4.5 4.25 2.85 2.55 100 10 0.1 1
Typ.
4.62 4.38 2.92 2.62 200
Max.
4.75 4.5 3.0 2.7 400 500
Unit
V
tPURST tRPD tF
(5) (5)
ms ns s ns V
tR(5) VRVALID
Note:
(5) This parameter is periodically sampled and not 100% tested.
CS/WDI vs. RESET/RESET Timing
CS/WDI tCST RESET tWDO tRST tWDO tRST
RESET
RESET/RESET Output Timing Symbol
tWDO
Parameter
Watchdog Time Out Period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 CS Pulse Width to Reset the Watchdog Reset Time Out
Min.
100 450 1 400 100
Typ.
200 600 1.4 200
Max.
300 800 2 400
Unit
ms ms sec ns ms
tCST tRST
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VTRIP Programming Timing Diagram
VCC (VTRIP)
VTRIP tTSU VP tTHD
WP tVPS tVPH tVPO
tPCS
CS
tRP
SCK
SI 06h 02h 01h or 03h
VTRIP Programming Parameters Parameter
tVPS tVPH tPCS tTSU tTHD tWC tVPO tRP VP VTRAN Vta1 Vta2 Vtr Vtv
Description
VTRIP Program Enable Voltage Setup time VTRIP Program Enable Voltage Hold time VTRIP Programming CS inactive time VTRIP Setup time VTRIP Hold (stable) time VTRIP Write Cycle Time VTRIP Program Enable Voltage Off time (Between successive adjustments) VTRIP Program Recovery Period (Between successive adjustments) Programming Voltage VTRIP Programmed Voltage Range Initial VTRIP Program Voltage accuracy (VCC applied-VTRIP) (Programmed at 25C.) Subsequent VTRIP Program Voltage accuracy [(VCC applied-Vta1)-VTRIP. Programmed at 25C.) VTRIP Program Voltage repeatability (Successive program operations. Programmed at 25C.) VTRIP Program variation after programming (0-75C). (Programmed at 25C.)
Min
1 1 1 1 10
Max
Unit
s s s s ms
10 0 10 15 1.7 -0.1 -25 -25 -25 18 5.0 +0.4 +25 +25 +25
ms s ms V V V mV mV mV
VTRIP programming parameters are periodically sampled and are not 100% tested.
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PACKAGING INFORMATION 8-Lead Miniature Small Outline Gull Wing Package Type M
0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) Typ.
R 0.014 (0.36) 0.118 0.002 (3.00 0.05)
0.030 (0.76) 0.0216 (0.55)
0.036 (0.91) 0.032 (0.81)
7 Typ.
0.040 0.002 (1.02 0.05)
0.008 (0.20) 0.004 (0.10)
0.0256" Typical
0.007 (0.18) 0.005 (0.13)
0.150 (3.81) Ref. 0.193 (4.90) Ref.
0.025" Typical 0.220"
FOOTPRINT
0.020" Typical 8 Places
NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
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X5043/X5045
PACKAGING INFORMATION 8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. 0.060 (1.52) 0.020 (0.51)
Half Shoulder Width On All End Pins Optional Seating Plane 0.150 (3.81) 0.125 (3.18)
0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
.073 (1.84) Max.
0.325 (8.25) 0.300 (7.62)
Typ. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
REV 1.1.2 5/29/01
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Characteristics subject to change without notice.
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X5043/X5045
PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1
0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7
0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25)
0.050 (1.27)
0.010 (0.25) X 45 0.020 (0.50)
0.050"Typical
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" Typical
FOOTPRINT
0.030" Typical 8 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.2 5/29/01
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Characteristics subject to change without notice.
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X5043/X5045
PACKAGING INFORMATION 14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05) See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.2 5/29/01
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Characteristics subject to change without notice.
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X5043/X5045
Ordering Information VCC Range
4.5-5.5V
VTRIP Range
4.5-4.75
Package
8-Pin PDIP 8L SOIC 8L MSOP 14L TSSOP
Operating Temperature Range
-40C-85C -40C-85C -40C-85C -40C-85C -40C-85C 0C-70C -40C-85C -40C-85C -40C-85C -40C-85C -40C-85C -40C-85C -40C-85C -40C-85C 0C-70C -40C-85C -40C-85C -40C-85C
Part Number RESET (Active LOW)
X5043PI-4.5A X5043S8I-4.5A X5043M8I-4.5A X5043V14I-4.5A X5043PI X5043S8 X5043S8I X5043M8I X5043V14I X5043PI-2.7A X5043S8I-2.7A X5043M8I-2.7A X5043V14I-2.7A X5043PI-2.7 X5043S8-2.7 X5043S8I-2.7 X5043M8I-2.7 X5043V14I-2.7
Part Number RESET (Active HIGH)
X5045PI-4.5A X5045S8I-4.5A X5045M8I-4.5A X5045V14I-4.5A X5045PI X5045S8 X5045S8I X5045M8I X5045V14I X5045PI-2.7A X5045S8I-2.7A X5045M8I-2.7A X5045V14I-2.7A X5045PI-2.7 X5045S8-2.7 X5045S8I-2.7 X5045M8I-2.7 X5045V14I-2.7
4.25-4.5
8-Pin PDIP 8L SOIC 8L MSOP 14L TSSOP
2.7-5.5V
2.85-3.0
8L PDIP 8L SOIC 8L MSOP 14L TSSOP
2.55-2.7
8-Pin PDIP 8L SOIC 8L MSOP 14L TSSOP
REV 1.1.2 5/29/01
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Characteristics subject to change without notice.
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X5043/X5045
Part Mark Information PDIP/SOIC X5043/45 X X Blank = 8-Lead SOIC P= 8 Pin Plastic DIP Blank = No suffix, 0C to +70C I = No Suffix; -40C to +85C A = -4,5A; 0C to +70C, IA = -4.5A; -40C to +85C F = -2.7; 0C to +70C G = -2.7; -40C to +85C FA = -2.7A; 0C to +70C GA = -2.7A; -40C to +85C TSSOP X5043/45 W X V = 14 Lead TSSOP MSOP YWW XXX AEP/AEY = No Suffix; -40C to +85C AEN/AEW = -4.5A; -40C to +85C AET/AFC = -2.7; -40C to +85C AER/AFA = -2.7A; -40C to +85C
X5043/X5045
Blank = 5V 10%, 0C to +70C, VTRIP = 4.25-4.5 AL = 5V10%, 0C to +70C, VTRIP = 4.5-4.75 I = 5V 10%, -40C to +85C, VTRIP = 4.25-4.5 AM = 5V 10%, -40C to +85C, VTRIP = 4.5-4.75 F = 2.7V to 5.5V, 0C to +70C, VTRIP = 2.55-2.7 AN = 2.7V to 5.5V, 0C to +70C, VTRIP = 2.85-3.0 G = 2.7V to 5.5V, -40C to +85C, VTRIP = 2.55-2.7 AP = 2.7V to 5.5V, -40C to +85C, VTRIP = 2.85-3.0
LIMITED WARRANTY
(c)Xicor, Inc. 2001 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. COPYRIGHTS AND TRADEMARKS Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM, E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
REV 1.1.2 5/29/01
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Characteristics subject to change without notice.
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